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TMC2250A
Matrix Multiplier
12 x 10 bit, 50 MHz Features
* Four user-selectable filtering and transformation functions: - Triple dot product (3 x 3) matrix multiply - Cascadeable 9-tap systolic FIR filter - Cascadeable 3 x 3-pixel image convolver - Cascadeable 4 x 2-pixel image convolver * 50 MHz (20ns) pipelined throughput * 12-bit input and output data, 10-bit coefficients * 6-bit cascade input and output ports in all filter modes * Onboard coefficient storage, with three-cycle updating of all nine coefficients
Applications
* * * * * * * Image filtering and manipulation Video effects generation Video standards conversion and encoding/decoding Three-dimensional image manipulation Medical image processing Edge detection for object recognition FIR filtering for communications systems
Description
The TMC2250A is a flexible high-performance nine-multiplier array VLSI circuit which can execute a cascadeable 9-tap FIR filter, a cascadeable 4 x 2 or 3 x 3-pixel image convolution, or a 3 x 3 color space conversion. All configurations offer throughput at up to the maximum guaranteed 50 MHz clock rate with 12-bit data and 10-bit coefficients. All inputs and outputs are registered on the rising edges of the clock. The 3 x 3 matrix multiply or color conversion configuration can perform video standard conversion (YIQ or YUV to RGB, etc.) or three-dimensional perspective translation at real-time video rates. The 9-tap FIR filter configuration, useful in Video, Telecommunications, and Signal Processing, features a 16-bit cascade input to allow construction of longer filters. The cascadeable 3 x 3 and 4 x 2-pixel image convolver functions allow the user to perform numerous image processing functions, including static filters and edge detectors. The 16-bit cascade input port facilitates two-chip 50 MHz cubic convolution (4 x 4-pixel kernel). The TMC2250A is fabricated in a sub-micron CMOS process and operates at clock speeds of up to 50 MHz over the full commercial (0C to 70C) temperature and supply voltage ranges. It is available in 120-pin Plastic Pin Grid Array (PPGA) packages, 120-lead Ceramic Pin Grid Array package (CPGA), 120-lead PQFP to PPGA package (MPGA) and 120-lead Plastic Quad FlatPack (PQFP). All input and output signals are TTL compatible.
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PRODUCT SPECIFICATION
TMC2250A
Functional Description
The TMC2250A is a nine-multiplier array with the internal bus structure and summing adders needed to implement a 3 x 3 matrix multiplier (triple dot product) a cascadeable 9-tap FIR filter, a 3 x 3-pixel convolver, or a 4 x 2-pixel convolver all in one monolithic circuit. With a 50MHz guaranteed maximum clock rate, this device offers video and imaging system designers a single-chip solution to numerous common image and signal-processing problems. The three data input ports (A, B, C) accept 12-bit two's complement integer data, which is also the format for the output ports (X, Y, Z) in the matrix multiply mode (Mode 00). In the filter configurations (Modes 01, 10, and 11) the cascade ports assume 12-bit integer, 4-bit fractional two's complement data on both input and output. The coefficient input ports (KA, KB, KC) are always 10-bit two's complement fractional. Table 1 details the bit weighting of the input and output data in all configurations.
KA1(1), KB3(4)
Indicates coefficient data stored in the specified one of the nine onboard coefficient registers KA1 through KC3, as shown in the block diagram for that mode, input during or before the specified clock rising edge (x).
X(1), Y(4), Z(6), CASOUT (6)
Indicated data available at that output port tDO after that specified clock rising edge (x). Applies to all output ports X11-0, Y11-0, Z11-0, and CASOUT15-0.
Numeric Format
Table 2 shows the binary weightings of the input and output ports of the TMC2250A. Although the internal sums of products could grow to 23 bits, in the matrix multiply mode (Mode 00) the outputs X, Y and Z are rounded to yield 12-bit integer words. Thus the output format is identical to the input data format. In the filter configurations (Modes 01, 10, and 11) the cascade output is always half-LSB rounded to 16 bits, specifically 12 integer bits and 4 fractional guard bits, with no overflow "headroom". The user is of course free to half-LSB round the output word to any size less than 16 bits by forcing a 1 into the bit position of the cascade input immediately below the desired LSB. In all modes, bit weighting is easily adjusted if desired by applying the same scaling correction factor to both input and output data words. If the coefficients are rescaled, the relative weightings of the CASIN and CASOUT ports will differ accordingly.
Operating Modes
The TMC2250A can implement four different digital filter architectures. Upon selection of the desired function by the user (MODE1-0), the device reconfigures its internal data paths and input and output buses appropriately. The output ports (XC, YC and ZC) are configured in all filter modes a 16-bit Cascade In and Cascade Out ports so that multiple devices can be connected to build larger filters. These modes are described individually below. The I/O function configurations for all four modes are shown in Table 1.
Data Overflow
As shown in Table 2, the TMC2250A's matched input and output data formats accommodate 0dB (unity) gain. Therefore, the user must be aware of input conditions that could lead to numeric overflow. Maximum input data and coefficient word sizes must be taken into account with the specific algorithm performed to ensure that no overflow occurs.
Definitions
The calculations performed by the TMC2250A in each mode are also shown below, utilizing the following notation:
A(1), B(5), C(2), CASIN(3)
Indicates the data word presented to that input port during the specified clock rising edge(x). Applies to all input ports A11-0, B11-0, C11-0, and CASIN15-0.
Table 1. Data Port Formatting by Mode
Mode 00 01 10 11 Inputs A11-0 B11-0 C11-0 KA9-0 KB9-0 KC9-0 A11-0 A11-0 A11-0 A11-0 B11-0 C11-0 KA9-0 KB9-0 KC9-0 B11-0 B11-0 NC NC Inputs/Output XC11-0 X11-0 YC11-8 Y11-8 Y7-4 Y7-4 NC NC NC Outputs YC3-0 Y3-0 ZC11-0 Z11-0
KA9-0 KB9-0 KC9-0 CASIN15-4 CASIN3-0 KA9-0 KB9-0 KC9-0 CASIN15-4 CASIN3-0
CASOUT3-0 CASOUT15-4 CASOUT3-0 CASOUT15-4 CASOUT3-0 CASOUT15-4
B11-0 C11-0 KA9-0 KB9-0 KC9-0 CASIN15-4 CASIN3-0
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PRODUCT SPECIFICATION
Table 2. Bit Weightings for Input and Output Data Words
Bit Weights Inputs All Modes Data A, B, C Coefficients KA, KB, KC -I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 . 211 210 29 28 27 26 25 24 23 22 21 20 . 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9
-K9 . K8 K7 K6 K5 K4 K3 K2 K1 K0
Modes 01, -CI15 CI14 CI13 CI12 CI11 CI10 CI9 CI8 CI7 CI6 CI5 CI4 . CI3 CI2 CI1 CI0 10, 11 CASIN Internal Sum Outputs Mode 00 X, Y, Z Modes 01, 10, 11 CASOUT -O11 O10 O9 O8 O7 O6 O5 O4 O3 O2 O1 O0 . X20 X19 X18 X17 X16 X15 X14 X13 X12 X11 X10 X9 . X8 X7 X6 X5 X4 X3 X2 X1 X0
- CO1 CO1 CO1 CO1 CO1 CO CO CO CO CO CO4 . CO CO CO CO CO15 4 3 2 1 0 9 8 7 6 5 3 2 1 0
Note: A minus sign indicates a two's complement sign bit.
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PRODUCT SPECIFICATION
TMC2250A
Pin Assignments
120 Pin Plastic Quad Flat Pack (MQFP), KE Package
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Name XC6 XC5 XC4 XC3 XC2 XC1 XC0 GND YC11 YC10 YC9 VDD YC8 Y7 Y6 GND Y5 Y4 YC0 VDD YC1 YC2 YC3 GND ZC0 ZC1 ZC2 ZC3 ZC4 ZC5 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Name ZC6 ZC7 ZC8 GND ZC9 ZC10 ZC11 KC0 KC1 KC2 KC3 GND KC4 KC5 KC6 VDD KC7 KC8 KC9 KB0 KB1 KB2 KB3 KB4 KB5 KB6 KB7 KB8 KB9 KA0 Pin 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 Name KA1 KA2 KA3 KA4 KA5 KA6 KA7 KA8 KA9 CWE1 CWE0 GND A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B0 B1 B2 CLK B3 B4 Pin 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Name B5 B6 B7 B8 B9 B10 B11 C0 C1 C2 C3 VDD C4 C5 C6 GND C7 C8 C9 C10 C11 MODE1 MODE0 GND XC11 XC10 XC9 VDD XC8 XC7
120 1
91 90
30 31
61 60
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TMC2250A
PRODUCT SPECIFICATION
Pin Assignments (continued)
120 Pin Plastic Pin Grid Array, H5 Package and 120 Pin Ceramic Pin Grid Array, G1 Package and 120 Pin Plastic Quad Flatpack to 120-Pin Pin Grid Array (MPGA)
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 C1 C2 C3 C4 Name XC7 XC9 XC10 MODE0 C11 C8 C7 C5 C3 C1 B10 B7 B4 XC4 XC5 XC8 XC11 MODE1 C9 C6 C4 C2 B11 B9 B6 B2 XC1 XC2 XC6 VDD Pin C5 C6 C7 C8 C9 C10 C11 C12 C13 D1 D2 D3 D11 D12 D13 E1 E2 E3 E11 E12 E13 F1 F2 F3 F11 F12 F13 G1 G2 G3 Name GND C10 GND VDD C0 B8 B5 B3 B1 YC11 XC0 XC0 CLK B0 A10 YC9 YC10 GND A11 A9 A8 Y7 YC8 VDD A7 A6 A5 Y5 Y6 GND Pin G11 G12 G13 H1 H2 H3 H11 H12 H13 J1 J2 J3 J11 J12 J13 K1 K2 K3 K11 K12 K13 L1 L2 L3 L4 L5 L6 L7 L8 L9 Name A3 A2 A3 Y4 YC0 VDD GND A0 A1 YC1 YC2 GND KA8 CWE1 CWE0 YC3 ZC0 ZC3 KA4 KA7 KA9 ZC1 ZC4 ZC6 GND KC0 GND VDD KB0 KB4 Pin L10 L11 L12 L13 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 Name KB8 KA1 KA5 KA6 ZC2 ZC7 ZC9 ZC11 KC2 KC4 KC6 KC9 KB2 KB5 KB9 KA2 KA3 ZC5 ZC8 ZC10 KC1 KC3 KC5 KC7 KC8 KB1 KB3 KB6 KB7 KA0
13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L MN KEY Top View Cavity Up
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PRODUCT SPECIFICATION
TMC2250A
Pin Descriptions
Pin Number Pin Name CPGA/PPGA/ MQFP MPGA Power VDD GND F3, H3, L7, C8, C4 12, 20, 46, 102, 118 Supply Voltage Ground The TMC2250A operates from a single +5V supply. All pins must be connected. The TMC2250A operates from a single +5V supply. All pins must be connected. Function Pin Description
E3, G3, J3, L4, 8, 16, 24, 34, L6, H11, C7, 42, 72, 106, C5 114 D11 88
Clock CLK System Clock The TMC2250A operates from a single system clock input. All timing specifications are referenced to the rising edge of clock. The TMC2250A will switch to the configuration selected by the user (as shown in Table 3) on the next clock. This registered control is usually static; however, should the user wish to switch between modes, the internal pipeline latencies of the device must be taken into account. Valid data will not be available at the outputs in the new configuration until enough clocks in the new mode have passed to flush the internal registers. Data presented to the coefficient input ports (KA, KB, and KC) will update three of the internal coefficient storage registers, as indicated by the simultaneous Coefficient Write Enable select, on the next clock. See Table 4 and the Functional Block Diagram. Data presented to the 12-bit registered data input ports A, B, and C are latched into the multiplier input registers for the currently selected configuration (Table 3). In all modes except Mode 00, new data are internally right-shifted to the next filter tap on each rising edge of CLK.
Controls MODE1,0 B4, A4 112, 113 Mode Control
CWE1,0
J12, J13
70, 71
Coefficient Write Enable
Input/Output A11-0 E11, D13, E12, 84, 83, 82, 81, Data Input A E13, F11, F12, 80, 79, 78, 77, F13, G13, 76, 75, 74, 73 G11, G12, H13, H12 B10, A11, B11, 97, 96, 95, 94, Data Input B C10, A12, B12, 93, 92, 91, 90, C11, A13, 89, 87, 86, 85 C12, B13, C13, D12 A5, C6, B6, A6, A7, B7, A8, B8, A9, B9, A10, C9 111, 110, 109, 108, 107, 105, 104, 103, 101, 100, 99, 98 Data Input C
B11-0
C11-0
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PRODUCT SPECIFICATION
Pin Descriptions (continued)
Pin Number Pin Name CPGA/PPGA/ MQFP MPGA KA9-0 Function Pin Description Data presented to the 10-bit registered coefficient input ports KA, KB and KC are latched three at a time into the internal coefficient storage register set indicated by the Coefficient Write Enable CWE1,0 on the next clock, as shown in Table 4.
K13, J11, K12, 69, 68, 67, 66, Coefficient L13, L12, K11, 65, 64, 63, 62, Input A1, A2, M13, M12, 61, 60 A3 L11, N13 M11, L10, 59, 58, 57, 56, Coefficient N12, N11, 55, 54, 53, 52, Input B1, B2, M10, L9, N10, 51, 50 B3 M9, N9, L8 M8, N8, N7, 49, 48, 47, 45, Coefficient M7, N6, M6, 44, 43, 41, 40, Input B1, B2, N5, M5, N4, L5 39, 38 B3
KB9-0
KC9-0
XC11-0
YC11-8 Y7-4 YC3-0 ZC11-0
In all modes except Mode 00, the x port and four bits of the Y output port are reconfigured as the 16-bit registered Cascade Input port CASIN15-0. Data presented to this input will be added to the weighted sums of the data words which were presented to the D1, E2, E1, F2 9, 10, 11, 13 CASIN3-0/ input ports (A, B and C). Output Y11-0 In the matrix multiply mode, data are available at the F1, G2, G1, H1 14, 15, 17, 18 Output7-4 only 12-bit registered output ports X, Y AND Z t after DO K1, J2, J1, H2 23, 22, 21, 19 CASOUT3-0/ every clock. These ports are reconfigured in the Output Y3-0 filtering modes as 16-bit Cascade Input and Output M4, N3, M3, 37, 36, 35, 33, CASOUT15-4/ ports.CASOUT15-0 In all modes except Mode 00, the Z port and four bits N2, M2, L3, 32, 31, 30, 29, Output Z11-0 of the Y output port are reconfigured as the 16-bit N1, L2, K3, 28, 27, 26, 25 registered Cascade Output port CASOUT15-0. M1, L1, K2
B4, A3, A2, B3, 115, 116, CASIN15-4/ A1, C3, B2, B1, 117, 119, Output X D3, C2, C1, D2 120, 1, 2, 3, 4, 5, 6, 7
Notes: 1. The output ports X, Y, Z and CASOUT, and input port CASIN are internally reconfigured by the device as required for each mode of the device. The multiple-function pins have names which are combinations of these titles, as appropriate. 2. The output drivers on pins XC11-0 and YC11-8 are not necessarily disabled until after the first rising edge of CLK following power-up. If these pins are to be tied to other output drivers, to each other, or to ground or VDD, the user should ensure that a clock pulse arrives within a few seconds of power-up, to avoid bus contention.
Table 3. Configuration Mode Word
MODE1,0 00 01 10 11 Configuration Mode 3 x 3 Matrix Multiply 9-Tap One Dimensional FIR 3 x 3 -Pixel Convolver 4 x 2 -Pixel Convolver
Table 4. Coefficient Write Enable Word
CWE1,0 00 01 10 11 Coefficient Set Selected Hold all registers Update KA1, KB1, KC1 Update KA2, KB2, KC2 Update KA3, KB3, KC3
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PRODUCT SPECIFICATION
TMC2250A
Table 5. Coefficient Input Ports
Input Port KA KB KC Registers Available KA1, KA2, KA3 KB1, KB2, KB3 KC1, KC2, KC3
multiplied by the appropriate stored coefficients. The three corresponding sums of products are available at the outputs five clock cycles after the input data are latched, and three new data words half-LSB rounded to 12 bits are then available every clock cycle. X(5)=A(1)KA1(1)+B(1)KB1(1)+C(1)KC1(1) Y(5)=A(1)KA2(1)+B(1)KB2(1)+C(1)KC2(1) Z(5)=A(1)KA3(1)+B(1)KB3(1)+C(1)KC3(1)
3 x 3 Matrix Multiplier (Mode 00)
This mode utilizes all six input and output ports in the basic configuration to realize a "triple dot product", in which each output is the sum of all three input words in that column
1 CLK
2
3
4
5
6
7
8
CWE
01
10
11
00
KA, KB, KC
K_1
K_2
K_3
DATA IN A, B, C
0
0
1.0
0
0
0
MODE CONTROL
00 KA1 + KB1 + KC1
X OUT KA2 + KB2 + KC2 Y OUT KA3 + KB3 + KC3 Z OUT
Figure 1. 3 x 3 Matrix Multiplier Impulse Response (Mode 00)
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PRODUCT SPECIFICATION
A
1 12 2 12 KA1 10 3 4 KA2 21 10 3 4 2 12 KA3 21 10 3 4 2 12
10
10
10 21
KA
10
B
12
1 2 12 KB1 10 3 4 KB2 21 10 3 4 2 12 KB3 21 10 3 4 2 12
10
10
10 21
KB
10
C
1 12 2 12 KC1 10 3 4 KC2 21 10 3 4 2 12 KC3 21 10 3 4 2 12
10
10
10 21
KC
10
RND 12 (MSB) 5 12 X
RND 12 (MSB) 5 12 Y
RND 12 (MSB) 5 12 Z
Figure 2. 3 x 3 Matrix Multiplier Configuration (Mode 00)
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PRODUCT SPECIFICATION
TMC2250A
9-Tap FIR Filter Mode (01)
The architecture for this configuration is shown in Figure 4. The user loads the desired coefficient set, presents input data to ports A and B simultaneously (most applications will wire the A and B inputs together), and receives the resulting 9sample response, half-LSB rounded to 16 bits, 5 to 13 clock cycles later. A new output data word is available every clock cycle. The figure shows that the input data are automatically rightshifted by one position through the row of multiplier input registers on every clock in anticipation of a new input data word. CASOUT(13) = A(9)KA3(9)+A(8)KA2(8)+A(7)KA1(7) +B(6)KB3(9)+B(5)KB2(8)+B(4)KB1(7) +B(3)KC3(9)+B(2)KC2(8)+B(1)KC1(7) +CASIN(10) Latency: Impulse in to center of 9-tap response =9 registers. Cascade In to Cascade Out=4 registers.
1 CLK
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CWE
01
10
11
KA, KB, KC
K_1
K_2
K_3
DATA IN A, B
1.0
MODE CONTROL
01
CASIN
Q13
CASOUT
KA3
KA2
KA1
KB3
KB2
KB1
KC3
KC2
KC1
Q13
Figure 3. 9-Tap FIR Filter Impulse Response (Mode 01)
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PRODUCT SPECIFICATION
A
12
1 2 12 KA1 10 3 4 KA2 21 10 3 4 2 12 KA3 21 10 3 4 2 12
10
10
10 21
KA
10
B
12
1
2
3
4 5 12 5 12 KB2 21 6 7 10 6 7 KB3 21 10 6 7 5 12
5 6 7 10
KB1
10
10
10 21
KB
10
C 8 12 KC1 10 9 10 KC 10 16 (MSB) CASIN (0 - 15) 16 21 5 `10000' HALF LSB ROUNDING 2, 5, 8, 11 3, 5, 6 8, 9, 11, 12 16 (MSB) 4 - 13 16 Z = CASOUT (0 - 15) 21 21 21 21 KC2 21 10 9 10 8 12 KC3 21 10 9 10 8 12
10
10
10 21
Figure 4. 9-Tap FIR Filter Configuration (Mode 01)
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PRODUCT SPECIFICATION
TMC2250A
3 x 3 Pixel Convolver (Mode 10)
This filter configuration accepts a 3 pixel-square neighborhood, side-loaded three pixels at a time through input ports A, B and C, and multiplies the 9 most recent pixel values by the coefficient set currently stored in the registers. These products are summed with the data presented to the cascade input, and a new 3-cycle impulse response, rounded to 16 bits, is available at the output port 5 to 7 clocks later, with a new output available on every clock cycle. The input pixel data are automatically shifted one location to the right through the three rows of multiplier input registers on every clock in anticipation of three new input data words, effectively sliding the convolutional window over one column in an image plane. CASOUT(7)= A(3)KA3(3)+A(2)KA2(2)+A(1)KA1(1) +B(3)KB3(3)+B(2)KB2(2)+B(1)KB1(1) +C(3)KC3(3)+C(2)KC2(2)+C(1)KC1(1) +CASIN(4) Latency: Impulse in to center of 3-tap response = 6 registers. Cascade In to Cascade Out=4 registers.
1 CLK
2
3
4
5
6
7
8
9
10
11
CWE
01
10
11
KA, KB, KC
K_1
K_2
K_3
DATA IN A, B, C
1.0
MODE 10
01
CASIN
Q17 K3 K2 K1
CASOUT
Q7
Kj = KAj + KBj + KCj
Figure 5. 3 x 3-Pixel Convolver Impulse Response (Mode 10)
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PRODUCT SPECIFICATION
A
12
1 2 12 KA1 10 3 4 KA2 21 10 3 4 2 12 KA3 21 10 3 4 2 12
10
10
10 21
KA
10
B
1 12 2 12 KB1 10 3 4 KB2 21 10 3 4 2 12 KB3 21 10 3 4 2 12
10
10
10 21
KB
10
C
1 12 2 12 KC1 10 3 4 KC2 21 10 3 4 2 12 KC3 21 10 3 4 2 12
10
10
10 21
KC
10 16 (MSB) 21 5 `10000' HALF LSB ROUNDING 2, 5 3, 5, 6 16 (MSB) 4-7 16 Z = CASOUT (0 - 15) 21 21 21 21
CASIN (0 - 15) 16
1
Figure 6. 3 x 3-Pixel Convolver Configuration (Mode 10)
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PRODUCT SPECIFICATION
TMC2250A
4 x 2-Pixel Cascadeable Convolver (Mode 11)
Similar to Mode 10, the 4 x 2 -Pixel convolver allows the use to perform full-speed cubic convolution with only two TMC2250A devices and the TMC2111A Pipeline Delay Register to synchronize the cascade ports (see the Applications Discussion section). Pixel data are side-loaded into ports A and B, multiplied by the onboard coefficients, summed with the cascade input, and half-LSB rounded to 16 bits. The four-cycle impulse response emerges at the cascade output port 5 to 8 clock cycles later. A new output word is available on every clock cycle. Note that Multiplier KC2 is not used in this mode and that its stored coefficient is ignored. As shown below, the column of input pixel data is automatically shifted one location to the right through the two rows of multiplier input registers on every clock in anticipation of two new input data words, effectively sliding the convolutional window over one column in an image plane. CASOUT(8)= A(4)KA3(4)+A(3)KA2(3)+A(2)KA1(2) +A(1)KB3(4)+B(4)KB3(4)+B(3)KB2(3) +B(2)KB1(2)+B(1)KC1(2)+CASIN(5)
1 CLK
2
3
4
5
6
7
8
9
10
11
CWE
01
10
11
00
KA, KB, KC
K_1
K_2
K_3
DATA IN A, B
1.0
MODE
11
CASIN
Q8 KA3 + KB3 KA1 + KB1 Q8 KA2 + KB2 KC1 + KC3
CASOUT
Figure 7. 4 x 2-Pixel Convolver Impulse Response (Mode 11)
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PRODUCT SPECIFICATION
A
12
1 2 12 KA1 10 3 4 KA2 21 10 3 4 2 12 KA3 21 10 3 4 2 12
10
10
10 21
KA
10 2
B
12
1 2 2 12 2 KB1 10 3 4 10 21 10 3 4 KB2 10 21 10 3 4 KB3 10 21 2 12 2 12
3 4
KB
10
C 3 12 KC1 10 4 5 KC 10 16 (MSB) CASIN (0 - 15) 16 1 5 16 (MSB) `10000' HALF LSB ROUNDING 4-8 16 Z = CASOUT (0 - 15) 21 21 2, 5 6 21 21 3, 5, 6, 7 21 KC2 21 10 0 12 KC3 21 10 6 7 5 12
10
10
10 21
Figure 8. 4 x 2-Pixel Convolver Configuration (Mode 11)
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PRODUCT SPECIFICATION
TMC2250A
tCY 1 CLK 2 3 4
tPWH 5
CWE
tPWL
KA, KB, KC tS X, Y, Z CASOUT tH PREVIOUS tHO
tD NEW
Figure 9. Input/Output Timing Diagram
VDD
VDD
p Digital Input n
p Digital Output n
GND
GND
Figure 10. Equivalent Digital Input Circuit
Figure 11. Equivalent Digital Output Circuit
Absolute Maximum Ratings (beyond which the device may be damaged)1
Parameter Supply Voltage Input Voltage Applied Voltage2 Externally Forced Current3,4 Short Circuit Duration (single output in HIGH state to ground) Operating, Ambient Temperature Junction Temperature Storage Temperature Lead Soldering Temperature (10 seconds) -65 -20 Min -0.5 -0.5 -0.5 -3.0 Typ Max 7.0 VDD + 0.5 VDD + 0.5 6.0 1 110 140 150 300 Unit V V V mA sec C C C C
Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device.
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Operating Conditions
Parameter VDD fCLK Power Supply Voltage Clock Frequency TMC2250A TMC2250A-2 TMC2250A-3 tPWH tPWL tS tH VIH VIL IOH IOL TA CLK pulse width, HIGH CLK pulse width, LOW Input Data Setup Time Input Data Hold Time Input Voltage, Logic HIGH Input Voltage, Logic LOW Output Current, Logic HIGH Output Current, Logic LOW Ambient Temperature, Still Air 0 6 8 6 2 2.0 0.8 -2.0 4.0 70 Min 4.75 Nom 5.0 Max 5.25 30 40 50 Units V MHz MHz MHz ns ns ns ns V V mA mA C
Electrical Characteristics
Parameter IDD Total Power Supply Current TMC2250A TMC2250A-2 TMC2250A-3 IDDU Power Supply Current, Unloaded VDD = Max, OE = HIGH, fCLK=Max TMC2250A TMC2250A-2 TMC2250A-3 IDDQ CPIN IIH IIL IOZH IOZL IOS VOH VOL Power Supply Current, Quiescent I/O Pin Capacitance Input Current, HIGH1
1
Conditions VDD = Max, CLOAD = 25pF, fCLK = Max
Min
Typ
Max 125 140 155 120 135 150 12
Units mA mA mA mA mA mA mA pF
VDD = Max, CLK = LOW 5 VDD = Max, VIN = VDD VDD = Max, VIN = 0 V VDD = Max, VIN = VDD VDD = Max, VIN = 0 V -20 IOH = Max, VDD = Min IOL = Max, VDD = Min 2.4
5 5 10 10 -80 0.4
A A A A mA V V
Input Current, LOW
Hi-Z Output Leakage Current, Output HIGH2 Hi-Z Output Leakage Current, Output LOW2 Short-Circuit Current Output Voltage, HIGH Output Voltage, LOW
Notes: 1. Except pins XC11-0, YC11-8. 2. Pins XC11-0, YC11-8.
REV. 1.0.2 10/25/00
17
PRODUCT SPECIFICATION
TMC2250A
Switching Characteristics
Parameter tDO tHO Output Delay Time Output Hold Time Conditions CLOAD = 25 pF CLOAD = 25 pF 3 Min Typ Max 15 Units ns ns
Application Notes
Performing Large-Kernel Pixel Interpolation
The Cascade Input and Output Ports of the TMC2250A allow the user to stack multiple devices to perform larger interpolation kernels with no decrease in pixel throughput. Figure 12 illustrates a basic application utilizing Mode 11 to realize a 4 x 4-pixel kernel, also called Cubic Convolution. This example utilizes the TMC2011A Variable-Length Shift Register to compensate for the internal latency of each TMC2250A. Alternatively, some applications may utilize RAM, FIFO's, or other methods to store multiple-line pixel data. In these cases the user may compensate for latency by simply offsetting the access sequencing of the storage devices.
A B
12 12
A 4 X 2 TMC2250A B CASOUT 16 CASIN
C D
12 12 3 X TMC2111A
A B
4 X 2 TMC2250A CASOUT 16 OUTPUT
Figure 12. Figure 12. Performing Cubic Convolution with Two TMC2250A's
Related Products
* * * * TMC2301 Image Resampling Sequencer TMC2302A Image Manipulation Sequencer TMC2249A Video Mixer TMC2242B Half-Band Filter
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TMC2250A
PRODUCT SPECIFICATION
Mechanical Dimensions
120-Lead CPGA Package
Inches Min. A A1 A2 oB oB2 D D1 e L L1 M N P Max. Millimeters Min. Max. Notes: Notes 1. Pin #1 identifier shall be within shaded area shown. 2. Pin diameter excludes solder dip finish. 3. Dimension "M" defines matrix size. 4. Dimension "N" defines the maximum possible number of pins. 2 2 SQ 5. Orientation pin is at supplier's option. 6. Controlling dimension: inch.
Symbol
.080 .160 .040 .060 .125 .215 .016 .020 .050 NOM. 1.340 1.380 1.200 BSC .100 BSC .110 .145 .170 .190 13 120 .003 --
2.03 4.06 1.01 1.53 3.17 5.46 0.40 0.51 1.27 NOM. 33.27 35.05 30.48 BSC 2.54 BSC 2.79 3.68 4.31 4.83 13 120 .076 --
3 4
A2 A1 L D e oB oB2 P
A
Top View Cavity Up
D1
Pin 1 Identifier
REV. 1.0.2 10/25/00
19
PRODUCT SPECIFICATION
TMC2250A
Mechanical Dimensions
120-Lead PPGA Package
Inches Min. A A1 A2 oB oB2 D D1 e L L1 M N P Max. Millimeters Min. Max. Notes: Notes 1. Pin #1 identifier shall be within shaded area shown. 2. Pin diameter excludes solder dip finish. 3. Dimension "M" defines matrix size. 4. Dimension "N" defines the maximum possible number of pins. 2 2 SQ 5. Orientation pin is at supplier's option. 6. Controlling dimension: inch.
Symbol
.080 .160 .040 .060 .125 .215 .016 .020 .050 NOM. 1.340 1.380 1.200 BSC .100 BSC .110 .145 .170 .190 13 120 .003 --
2.03 4.06 1.01 1.53 3.17 5.46 0.40 0.51 1.27 NOM. 33.27 35.05 30.48 BSC 2.54 BSC 2.79 3.68 4.31 4.83 13 120 .076 --
3 4
A2 A1 L D e oB oB2 P
A
Top View Cavity Up
D1
Pin 1 Identifier
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REV. 1.0.2 10/25/00
TMC2250A
PRODUCT SPECIFICATION
Mechanical Dimensions
120-Lead Metric Quad Flat Package to Pin Grid Array Package (MPGA)
Symbol A A1 A2 A3 oB oB2 D D1 e L M N Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Pin #1 identifier shall be within shaded area shown. 2. Pin diameter excludes solder dip finish. 3. Dimension "M" defines matrix size. 4. Dimension "N" defines the maximum possible number of pins. 5. Orientation pin is at supplier's option. 2 2 SQ 6. Controlling dimension: inch.
.309 .311 .145 .155 .080 .090 .050 TYP. .016 .020 .050 NOM. 1.355 1.365 1.200 BSC .100 BSC .175 .185 13 120
7.85 7.90 3.68 3.94 2.03 2.29 1.27 TYP. 0.40 0.51 1.27 NOM. 34.42 34.67 30.48 BSC 2.54 BSC 4.45 4.70 13 120
3 4
A A1 L A3 oB2 oB e A2
D e
Fairchild TMC2250A
D1
Pin 1 Identifier
REV. 1.0.2 10/25/00
21
PRODUCT SPECIFICATION
TMC2250A
Mechanical Dimensions
120-Lead MQFP Package
Inches Min. A A1 A2 B C D/E D1/E1 e L N ND
ccc
Symbol
Millimeters Min. Max.
Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. Controlling dimension is millimeters. 3. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be .08mm (.003in.) maximum in excess of the "B" dimension. Dambar cannot be located on the lower radius or the foot. 4. "L" is the length of terminal for soldering to a substrate. 5. "B" & "C" includes lead finish thickness.
Max.
-- .154 .010 -- .125 .144 .018 .012 .009 .005 1.219 1.238 1.098 1.106 .0315 BSC .026 .037 120 30 0 -- 7 .004
-- 3.92 .25 -- 3.17 3.67 .45 .30 .23 .13 30.95 31.45 27.90 28.10 .80 BSC .65 .95 120 30 0 -- 7 .10
3, 5 5
4
.20 (.008) Min. D D1 e PIN 1 IDENTIFIER E 0.063" Ref (1.60mm) Lead Detail E1 0 Min. .13 (.005) R Min. .13/.30 R .005/.012 C L
See Lead Detail A A2 B A1 Seating Plane Base Plane -CLEAD COPLANARITY ccc C
22
REV. 1.0.2 10/25/00
PRODUCT SPECIFICATION
TMC2250A
Ordering Information
Product Number TMC2250AG1C TMC2250AG1C2 TMC2250AG1C3 TMC2250AH5C TMC2250AH5C2 TMC2250AH5C3 TMC2250AH6C TMC2250AH6C2 TMC2250AH6C3 TMC2250AKEC TMC2250AKEC2 TMC2250AKEC3 Temperature Range 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C Speed Grade 30 MHz 40 MHz 50 MHz 30 MHz 40 MHz 50 MHz 30 MHz 40 MHz 50 MHz 30 MHz 40 MHz 50 MHz Screening Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Package 120 Pin Ceramic Pin Grid Array 120 Pin Ceramic Pin Grid Array 120 Pin Ceramic Pin Grid Array 120 Pin Plastic Pin Grid Array 120 Pin Plastic Pin Grid Array 120 Pin Plastic Pin Grid Array 120 Lead Metric Quad Flatpack to Pin Grid Array 120 Lead Metric Quad Flatpack to Pin Grid Array 120 Lead Metric Quad Flatpack to Pin Grid Array 120 Lead Plastic Quad Flatpack 120 Lead Plastic Quad Flatpack 120 Lead Plastic Quad Flatpack Package Marking 2250AG1C 2250AG1C2 2250AG1C3 2250AH5C 2250AH5C2 2250AH5C3 N/A N/A N/A 2250AKEC 2250AKEC2 2250AKEC3
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
10/25/00 0.0m 002 Stock#DS30002250A 2000 Fairchild Semiconductor Corporation

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